A magnetoresistive random access memory (hereinafter referred to as an MRAM) is known, which stores data by controlling a magnetization direction of a memory element. The MRAM has several types depending on a memory method of a magnetization direction.
A first prior art (U.S. Pat. No. 6,545,906) discloses a technique of a toggle-type magnetoresistive random access memory (hereinafter referred to as a toggle MRAM). This toggle MRAM employs a magnetic tunneling junction (MTJ) element in which a laminated free layer is used for a memory element thereof. The toggle MRAM is different from a conventional and typical MRAM in terms of a memory cell configuration and a principle of a write operation, and characterized by a property of excellent selectivity of a memory cell in a write operation. Details will be explained below.
FIGS. 1 and 2 are cross sectional views showing configurations of typical magnetic tunneling junction elements used for the toggle MRAM. This magnetic tunneling junction element 125 is provided between a first wiring 110 and a second wiring 101. The magnetic tunneling junction element 125 includes an anti-ferromagnetic layer 109, a pin layer 108, a non-magnetic metal layer 107, a reference layer 106, a tunnel layer 105, a first free layer 104, a non-magnetic metal layer 103, and a second free layer 102 on the first wiring 110 in this order, and is connected to the second wiring 101.
The magnetic tunneling junction element 125 is characterized in that the first free layer 104 and the second free layer 102 are equal in a film thickness and are laminated through the non-magnetic metal layer 103. The pin layer 108 and the reference layer 106 are also laminated through the non-magnetic metal layer 107. A magnetization direction of the pin layer 108 and the reference layer 106 is firmly fixed at the time of fabrication. A magnetic field generated by write currents flowing in the first wiring 110 and the second wiring 101 is capable of changing a first free layer magnetization direction belonging to the first free layer 104 and a second free layer magnetization direction belonging to the second free layer 102. The first and second free layer magnetization directions are stable in an anti-parallel state by being inverted for 180 degrees from each other. If one of the free layer magnetization directions is reversed, the other free layer magnetization direction should be reversed so as to retain the anti-parallel state.
A sense operation principle in the toggle MRAM is the same as a sense operational principle in the conventional and typical MRAM. That is, the sense operation is carried out by detecting a tunnel current passing through the tunnel film 105 provided between the first free layer 104 and the reference layer 106. If the first free layer magnetization direction is in the parallel state to a reference layer magnetization direction belonging to the reference layer 106, the tunnel current is increased in comparison with the anti-parallel state, which means a magnetoresistance (MTJ resistance) is decreased. Information stored in the memory cell is read out by utilizing this characteristic. For convenience of explanation, it is defined as “1” if the magnetoresistance has a high resistance value Rmax (tunnel current mm.) (FIG. 1, and it is defined as “0” if the magnetoresistance has a low resistance value Rmin (tunnel current max.) (FIG. 2).
In a conventional MRAM disclosed in a second prior art (U.S. Pat. No. 6,392,923), for example, a reference cell is constituted by using a plurality of memory cells that are programmed in advance so that a combined resistance value Rref is made to be Rmin<Rref<Rmax. Information stored in the memory cells is sensed at a high speed by comparing a resistance value of a selected memory cell with the resistance value Rref of the reference cell.
According to the first prior document, a plane layout of the memory cell of the toggle MRAM is different from that of the conventional and typical MRAM. FIG. 3 is a top surface view showing the plane layout of the memory cell in the first prior document. The toggle MRAM is characterized in that a magnetization easy axis direction of a magnetic tunneling junction element is arranged in neither an X direction to which the first wiring ((write) word line) extends nor a Y direction to which the second wiring (bit line) extends, and arranged so as to be in about 45° direction from the X and Y directions. This is in consideration of allowing a toggle operation mentioned below to be carried out easily.
The write operation principle of a toggle MRAM, which is different from that of the conventional and typical MRAM, will be explained next. In a write operation of the conventional and typical MRAM, a free layer magnetization direction is determined by controlling a write current direction of a bit line in accordance with information to be written. On the other hand, in the write operation of the toggle MRAM disclosed in the first prior art, a read-out operation is executed in a selected memory cell in advance, and then, whether or not to change the first and second free layer magnetization directions (whether or not to execute the toggle operation) is determined based on the read-out information and the information to be written. That is, the toggle operation will not be executed if the read-out information (“0” or “1”) is equal to the information to be written (“0” or “1”), and the toggle operation will be executed if the read-out information is different from the information to be written.
FIGS. 4 to 6 are diagrams showing the toggle operation principle in the toggle MRAM according to the first prior art. FIG. 4 is a timing chart showing a timing of a write current IWL and a write current IBL in the toggle operation. FIGS. 5 and 6 are diagrams showing changes of the first and second free layer magnetization directions in the toggle operation. Thin arrows indicate the second free layer magnetization direction and thick arrows indicate the first free layer magnetization direction. FIG. 5 is the case that a data “1” is being written to the magnetic tunneling junction element in which data “0” is stored. FIG. 6 is the case that a data “0” is being written to the magnetic tunneling junction element in which data “1” is stored.
Referring to FIG. 3, in the toggle operation, the write current IWL is supplied to the write word line at a time t1. The write current IBL is supplied to the bit line at a time t2. The write current IWL is stopped at a time t3. Then, the write current IBL is stopped at a time t4. A series of the current controls mentioned above causes a rotating magnetic field to be applied at a cross point between a selected (write) word line to which the write current IWL is supplied and a selected bit line to which the write current IBL is supplied, enabling to write data by rotating (changing) the first and second free layer magnetization directions.
Referring to FIGS. 5 and 6, in the magnetic tunneling junction element, the first and second free layer magnetization directions start rotate at the time t1. One of the first and second free layer magnetization directions exceeds a magnetization difficult axis at the time t2. Another of the first and second free layer magnetization directions also exceeds the magnetization difficult axis at the time t3. In this manner, the first and second free layer magnetization directions are thus made one revolution, respectively, in a spin flop state. That is, the magnetic tunneling junction element is rewritten (toggled) to bring a state of “1” if an initial state thereof is “0”, and to bring a state of “0” if an initial state thereof is “1”.
FIG. 7 is a graph showing a relationship among the write current IWL, the write current IBL and the memory cell (magnetic tunneling junction element) to be toggled. A vertical axis indicates the write current IWL and a horizontal axis indicates the write current IBL. A solid circle corresponds to the selected cell, open circles correspond to a half selected cell (a cell of which any one of the write word line and the bit line is in a common with the selected cell), and an X mark corresponds to a non-selected cell. A region shown as “TOGGLE” means a region in which the toggle operation is observed. A region shown as “No Switching” means a region in which the toggle operation is not observed.
The toggle MRAM has a very low possibility of making an error writing because the magnetic field is applied only in a single direction to a memory cell in the half selected state (the open circles in the figure) placed on the selected (write) word line or the selected bit line. Therefore, it is not necessary to strictly control a value of the write current, and a write margin is significantly improved in comparison with the conventional and typical MRAM.
As explained above, the write operation in a typical MRAM is executed by controlling the free layer magnetization of the magnetic tunneling junction element by the write current direction corresponding to information to be written. On the other hand, in the case of the toggle MRAM, the write operation is executed by whether or not to reverse (to toggle) the free layer magnetization directions. It is therefore necessary to sense stored information of the selected memory cell before executing the toggle operation. The sense operation in a general cell placed in a user area is executed by comparing a resistance value of a selected cell with a resistance value of a reference cell. Accordingly, the write operation in the general cell is capable if it is decided whether or not to execute the toggle operation on the basis of the information to be written and the latest sense result. Meanwhile, it is necessary to write (program) known reference information in advance with high reliability to the reference cell which becomes a reference of a general cell at the time of supplying a power source or the like. However, because reference information required writing the reference cell does not exist, it is impossible to sense the stored information in the same manner with the general cell.
In conjunction with the above technique, an information reproducing method is disclosed in Japanese Laid Open Patent Application JP 2002-140889A. This technique is an information reproducing method from a ferromagnetic memory including a variable resistor composed with magnetic material. The variable resistor includes a hard layer to store information by a magnetization direction, a non-magnetic layer, and a soft layer composed with magnetic material having a smaller coercive force than that of the hard layer. The soft layer is first initialized while detecting and holding a resistance value of the variable resistor. When a magnetization of the soft layer is reversed next, the resistance value of the variable resistor is detected and compared with the resistance value which has been held, so that information stored in the hard layer is reproduced based on an increase or a decrease of the resistance value.
In conjunction with the above technique, a read-out circuit of a semiconductor memory device is disclosed in Japanese Laid Open Patent Application JP 2003-257173A. This technique is a read-out circuit of a semiconductor memory device in which a memory cell array is composed with memory cells having two memory states of a first memory state with a relatively small resistance value and a second memory state with a relatively large resistance value. The read-out circuit includes a pre-amplifier, a voltage control oscillator, a counter, count value memory means, and determination means. The pre-amplifier detects a current supplied from a selected cell which is selected among the memory cells, and amplified and converts the detected current to a voltage. The voltage control oscillator oscillates frequency proportional to the output voltage of the pre-amplifier. The counter counts the number of pulses supplied from the voltage control oscillator. The count value memory means stores an output value of the counter. The determination means receives the output value of the counter and that of the count value memory means, and determines a memory state of the selected cell.